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PD - 97206A
AUTOMOTIVE MOSFET
IRF1405ZS-7PPbF IRF1405ZL-7PPBF
Features
l l l l l l
HEXFET(R) Power MOSFET
D
Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free
VDSS = 55V RDS(on) = 4.9m
G S
Description
Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
S (Pin 2, 3, 5, 6, 7) G (Pin 1)
ID = 120A
D2Pak 7 Pin
TO-263CA 7 Pin
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS EAS EAS (tested) IAR EAR TJ TSTG Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (See Fig. 9) Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current
Max.
150 100 120 590 230 1.5 20 250 810 See Fig.12a,12b,15,16 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A
c
Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy (Thermally Limited) Single Pulse Avalanche Energy Tested Value Avalanche Current
W W/C V mJ A mJ C
c
h
d
Repetitive Avalanche Energy Operating Junction and Storage Temperature Range
g
Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Thermal Resistance
RJC RCS RJA RJA Junction-to-Case
j
Parameter
Typ.
--- 0.50
Max.
0.65 --- 62 40
Units
C/W
Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
j
Junction-to-Ambient (PCB Mount, steady state)
ij
--- ---
HEXFET(R) is a registered trademark of International Rectifier.
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1
12/07/06
IRF1405ZS/L-7PPbF
Static @ TJ = 25C (unless otherwise specified)
Parameter
V(BR)DSS VDSS/TJ RDS(on) SMD VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. Typ. Max. Units
55 --- --- 2.0 150 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.054 3.7 --- --- --- --- --- --- 150 37 64 16 140 170 130 4.5 7.5 5360 1310 340 6080 920 1700 --- --- 4.9 4.0 --- 20 250 200 -200 230 --- --- --- --- --- --- --- --- --- --- --- --- --- --- pF
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 88A V VDS = VGS, ID = 150A S VDS = 25V, ID = 88A A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V nC ID = 88A VDS = 44V VGS = 10V ns VDD = 28V ID = 88A RG = 5.0 VGS = 10V D nH Between lead,
e
e d
6mm (0.25in.) from package
G
S and center of die contact VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 44V, = 1.0MHz VGS = 0V, VDS = 0V to 44V
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 63 160 150 A 590 1.3 95 240 V ns nC
Conditions
MOSFET symbol showing the integral reverse
G D
S p-n junction diode. TJ = 25C, IS = 88A, VGS = 0V TJ = 25C, IF = 88A, VDD = 28V di/dt = 100A/s
e
e
Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L=0.064mH, RG = 25, IAS = 88A, VGS =10V. Part not recommended for use above this value. Pulse width 1.0ms; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
R is measured at TJ of approximately 90C. Solder mounted on IMS substrate.
2
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IRF1405ZS/L-7PPbF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
4.5V
10
4.5V
10
60s PULSE WIDTH
1 0.1 1 Tj = 25C 10 1 100 1000 0.1 1
60s PULSE WIDTH
Tj = 175C 10
100
1000
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
Gfs, Forward Transconductance (S)
150 125 T J = 25C 100 75 50 25 0 0 25 50 75 100 125 150 175 200 ID,Drain-to-Source Current (A) V DS = 10V 300s PULSE WIDTH T J = 175C
ID, Drain-to-Source Current ()
100 T J = 175C 10 T J = 25C 1 VDS = 25V 60s PULSE WIDTH 0 2 4 6 8 10 12
0.1
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance vs. Drain Current
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3
IRF1405ZS/L-7PPbF
100000
C oss = C ds + C gd
10000 Ciss Coss 1000 Crss
VGS, Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd
12.0 ID= 88A 10.0 8.0 6.0 4.0 2.0 0.0 VDS= 44V VDS= 28V
C, Capacitance(pF)
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
50
100
150
200
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000
10000 1000 100 1msec 10 1 0.1 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Tc = 25C Tj = 175C Single Pulse DC 10msec OPERATION IN THIS AREA LIMITED BY R DS(on) 100sec
T J = 175C 100
10
T J = 25C
1 0.0 0.5 1.0 1.5
VGS = 0V 2.0 2.5
VSD, Source-to-Drain Voltage (V)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF1405ZS/L-7PPbF
150 125
ID, Drain Current (A)
RDS(on) , Drain-to-Source On Resistance (Normalized)
2.5
ID = 88A VGS = 10V
2.0
100 75 50 25 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
1.5
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T J , Junction Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Normalized On-Resistance vs. Temperature
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20 0.10 0.05 0.02 0.01
J J 1
R1 R1 2
R2 R2
R3 R3 3 C 3
0.01
Ri (C/W) 0.1707 0.1923 0.2885
i (sec) 0.000235 0.000791 0.008193
1
2
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1405ZS/L-7PPbF
15V
1000
EAS , Single Pulse Avalanche Energy (mJ)
DRIVER
VDS
L
800
ID 14A 23A BOTTOM 88A TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
600
0.01
400
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
200
0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy vs. Drain Current
10 V
QGS VG QGD
4.5
VGS(th) Gate threshold Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
50K 12V .2F .3F
ID = 150A ID = 250A ID = 1.0mA ID = 1.0A
D.U.T. VGS
3mA
+ V - DS
T J , Temperature ( C )
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage vs. Temperature
6
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IRF1405ZS/L-7PPbF
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100 0.01 10 0.05 0.10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.1 1.0E-06
1.0E-05
1.0E-04 tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 15. Typical Avalanche Current vs.Pulsewidth
300 250 200 150 100 50 0 25 50
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 88A
75
100
125
150
175
Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 16. Maximum Avalanche Energy vs. Temperature
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IRF1405ZS/L-7PPbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* dv/dt controlled by RG * Driver same type as D.U.T. * I SD controlled by Duty Factor "D" * D.U.T. - Device Under Test
V DD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
*
VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V DS V GS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
D.U.T.
+
-V DD
Fig 18a. Switching Time Test Circuit
VDS 90%
10% VGS
td(on) tr t d(off) tf
Fig 18b. Switching Time Waveforms
8
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IRF1405ZS/L-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
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9
IRF1405ZS/L-7PPbF
D2Pak - 7 Pin Part Marking Information
AIR
D2Pak - 7 Pin Tape and Reel
10
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IRF1405ZS/L-7PPbF
TO-263CA 7 Pin Long Leads Package Outline
Dimensions are shown in millimeters (inches)
Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IRs Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 12/06
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11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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